Digital Design and Modeling with VHDL and Synthesis (Systems)

When first starting VHDL, I picked up this book and found it somewhat hard to follow. After some initial reading, I had to give up and put it on the shelf, and then began looking for other easy books to read. One after another, I finally bought a dozen of VHDL books, some of which I wished I had not. Among these books, I found that Andrew Rushton's "VHDL for Logic Synthesis 2nd" is a wonderful beginner's reading; I got some VHDL coding skills with "Essential VHDL, RTL Syntheses Done Right" by Sundar Rajan; Peter Ashenden's "Designer's Guide to VHDL" is good, but too thick to read from cover to cover; Kevin Skahill taught me important programmable logic concept with "VHDL for Programmable Logic"...After all these books, I still felt uncertain, lack of something. Then I came to understand that I needed some good real world design examples, something real, not just demo. I took this book again from the shelf, Woo, totally different now! This was what I needed now. The author doesn't waste time telling me which is better, Verilog or VHDL, or which is the more useful package, std_logic_arith or numeric_std. He just shows me with excellent examples what real world engineers do in their projects; so I gradually understand what I will do in face with real world problems. By now I learnt to know that when possible I'll use std_logic_arith package in my design in spite of its proprietary, because by doing so one can get rid of worrying about type conversions at the ports, and therefore avoid possible mistakes in the code; I know how to use logic hiding, source sharing, variable using skills to get better designs. The author provides more examples in his new book: "Digital Systems Design With Vhdl and Synthesis: An Integrated Approach", but after reading them over and again, I still think the first book is better. In my opinion, it's really concise and to the point. Though there are some minor problems with it, such as incomplete references, lack of important package listings, I give it solid five stars!

I agree with previous author that this book is not for beginner and the intention of this book is not for beginner. I will recommend that a beginner read other VHDL books and get familiar with VHDL then read "VHDL - Coding and Logic Synthesis with Synopsys" by Weng Fook Lee and then this book if you want to go into logic synthesis.The weakness of this book is that it is a little verbose and some of the sentences are not clear. Also the typesetting is not as good as other books, but considering all those great content (and thick too) along with a cheap price, it is an excellent book!

KC Chang did it again! I have Mr. Chang's 1st edition of this text, and I have found it to be an excellent reference material for VHDL design. I read through the text, and I have discovered that his method of explination is both CLEAR and CONCISE. In other words, it is to the point. The codes are explained step-by-step and relevant topics are given further explination...this is extremely helpful for those designing with VHDL. It is a wise investment for my technical career in high speed digital design. The text from Kevin Skahill is another text that complements this one. Bhaskers is another good complement also. Choose any of the three...THEY ARE ALL GOOD.

The book organization is unique in that the codes are all complete from beginning to end with line numbers. The author explains the relevant codes line by line. However, as the book progresses, he explains less details of the codes. Another unique feature (the best feature) is that every code comes with synthesized circuits along with synthesis commands of how to optimize for different goals (i.e. best timing or best area). The practical examples are real life examples (i.e. microprocessor, FIFO, FIR filter, DRAM etc.) The reader will also get design fundamentals of the above examples. Overall, an excellent book!